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#1
11-27-2011, 01:09 AM
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cs501 2011 final term spring term
Q1 what is assembler and what is it important in assembly language (2)
Q2 what is program instruction control? (2) Q3 define virtual memory (2) Q4 difference between higher level language and assembler (3) Q5define ISA Q6 convert (390)10 into base 16 (5) Q7 define pipelining(5) Q8 define the type of error control(5) Q9 define booth recording (2) Ppr was so e.z mcqs past paperz me se they majority 40 MCQ's and 12 Short Questions including 6 of 2 marks 4 of 3 marks and 2 of 5 marks Mostly MCQ's from Lecture # 28 to 40 i suggest u to study the lectures related to Interrupts & DMA i think there is only 2 or 3 mcq's from midterm course don't bother ur time to study midterm course Following is the subjective portion of my paper. 1. Where is TCP/IP is used. 2. Usage of DMA 3. How to right RTL 4. What you mean by ISA (Instruction Set Architecture) 5. Define the different types of Instructions used in FALCON-E 6. Uni-bus interaction with I/O subsystem 7. Conversion from base 10 number into base 16 number (hex) 8. Define one benifit and one Drawback of Cache. 9. Define different level of RAID and 10. What are the similarities at Level 2 and Level 3 of the RAID my paper of 15-06-2011 5 marks questions issues of error control cache definition and management structural RTL of instruction fetch connectionless and connection oriented communication difference 3 marks questions functions of virtual memory cache hit and cache miss branch and structural hazard DMA uses 2 marks questions floating point overflow uses of virtual memory difference between throughput and latency which method is used for transfer between memory and I/O ports without the interruption of CPU? 40 MCQS from past papers and handout and 80 marks paper Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines a) How many sets are there in the cache? b) How many bits of address are required to select a set in cache? Q2 convert the hexadecimal number B316 to base 10 5Marks Q3 what do you know about " booth pair recording 3marks Q.4 assembler symbol table note.3-marks: Q.5 configuration of 1x8 memory cell .3marks Q.6 Single detached DMA 5marks Q.7 what is hardisk 2 marks Q.8 difference bw connection oriented and connection less Q.9 pipeline disadvantage 3 marks My Paper of CS501 19.07.2011 What is DMA? Differentiate between throughput and latency? Describe six attributes of SRC Processor? Briefly Describe Classification of Networks? Write note on Pipelining? What is virtual memory? How does work Associative Mapping? How does work set Associative Memory? How overflow is represented in case of floating point? 4 question from DMA nad Interrupt I/O what is pipelining ?with or without Consider a LAN, using bus topology. If we replace the bus with a switch, what change will occur in such a configuration? floating poit numerical qs 5 marks base 10 sai 2 question the what is the purpose of control unit? 2 2. Booth pair Recording? 2 3. which technique allows certain hardware subsystems within a computer to access system memory for read/write independently of the main CPU.? 4. 64KB direct-mapped cache line length 32, determine number of bits in the address? 5. similarities and diff. between RAID level 4 and 5 6. consider a 4 way set-associative cache with 256KB capacity and 32 byte lines i. find sets in the cache ii. and bit address required to select a set . 7. advantage of linker in the development of assembly language program 8. Steps used for floating point addition and subtraction. 9. diff b/w distributed computing and computer Network and classifications of networks 10. software polling and drawbacks of software polling and daisy chain 11. cache and it's management 12. compare RISC and CISC s501........ 2 marks............ - PROM - platter in hard disk - differentiate PC n IR -aik aur v tha q. wo yaad nae 3 marks......... - differentiate computer netwrk and distributed computing - EPROM - structral RTL for move instruction for uni bus - find average rotational latency if disk rotate at 15,ooorpm -5 marks............. - SRC assembly program for z=4(a+b)-8(c-27) - wat is mant by abstraction from user detail by operating system - compare 1*8 memory cell in 1D with 4*8 memory in 2D Q1 what is assembler and what is it important in assembly language (2) Q2 what is program instruction control? (2) Q3 define virtual memory (2) Q4 difference between higher level language and assembler (3) Q5define ISA Q6 convert (390)10 into base 16 (5) Q7 define pipelining(5) Q8 define the type of error control(5) Q9 define booth recording (2) Ppr was so e.z mcqs past paperz me se they majority Q1 ( Marks: 5 ) Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines a) How many sets are there in the cache? b) How many bits of address are required to select a set in cache? Q2 convert the hexadecimal number B316 to base 10 5Marks Q3 what do you know about " booth pair recording 3marks Q.4 assembler symbol table note.3-marks: Q.5 configuration of 1x8 memory cell .3marks Q.6 Single detached DMA 5marks Q.7 what is hardisk 2 marks Q.8 difference bw connection oriented and connection less Q.9 pipeline disadvantage 3 marks 40 MCQ's and 12 Short Questions including 6 of 2 marks 4 of 3 marks and 2 of 5 marks Mostly MCQ's from Lecture # 28 to 40 i suggest u to study the lectures related to Interrupts & DMA i think there is only 2 or 3 mcq's from midterm course don't bother ur time to study midterm course Following is the subjective portion of my paper. 1. Where is TCP/IP is used. 2. Usage of DMA 3. How to right RTL 4. What you mean by ISA (Instruction Set Architecture) 5. Define the different types of Instructions used in FALCON-E 6. Uni-bus interaction with I/O subsystem 7. Conversion from base 10 number into base 16 number (hex) 8. Define one benifit and one Drawback of Cache. 9. Define different level of RAID and 10. What are the similarities at Level 2 and Level 3 of the RAID. my paper of 15-06-2011 5 marks questions issues of error control cache definition and management structural RTL of instruction fetch connectionless and connection oriented communication difference 3 marks questions functions of virtual memory cache hit and cache miss branch and structural hazard DMA uses 2 marks questions floating point overflow uses of virtual memory difference between throughput and latency which method is used for transfer between memory and I/O ports without the interruption of CPU? 40 MCQS from past papers and handout and 80 marks paper 
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#2
11-27-2011, 06:57 AM
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Good thread,thx!
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Linear Mode
