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Mostly mcqs were from the file which is attached here must prepare it .
And here is the subjective portion What is relation b/w data path and control unit in SRC processors…….2marks Define Pre-fetching……….2marks Write the structural RTL for “ in ra, rb” ……….3marks What is difference between Latency and Throughput……3marks Write the Structural RTL for “call ra, rb”……….5marks What are the pipeline problems. Describe each briefly…. 5marks Q no 1 Define Control unit. (2 marks) Q no 2 How can you define Microprogram (2 marks) Q no 3 Instruction fetch say tha yad nahin (3 marks) rel Ra Q no 4 what is the utility of reset operation when it is required (3 marks) Q no5 what are the types of SRC?Name them? also explain its format? (5 marks) Total 26 Questions from which 20 is MCQ and 2 Question of 2 marks and 2 of 3 marks and remaining 2 of 5 marks. What is the instruction length of the SRC processor? 8 bits 16 bits 32 bits 64 bits Which one of the following is the memory organization of FALCON-E processor? 28 * 8 bits 216 * 8 bits 232 * 8 bits 264 * 8 bits ________ operation is required to change the processor’s state to a known, defined value. Change Reset Update None of the given There are _________ types of reset operations in SRC Two Three Four Five _____________ controller controls the sequence of the flow of microinstructions. Multiplexer Microprogram ALU None of the given There are remaining mcq’s mostly from instructions working. Subjective Question: How can you define microprogram? (2 Marks) A question about to define the shift right instruction? (2 Marks) What is the utility of reset operation and when it is required? (3 Marks) Structural RTL instructions definition? (3 Marks) Write the Structural RTL description for un-conditional jump instruction for uni-bus data path implementation. (5 Marks) Define two hazard in pipelining and how can to overcome these. (5 Marks) |
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Linear Mode


