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11-27-2011, 01:00 AM
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cs501 final term 2011
mcqs were very tough 10 to RAID me se thay or wo jo handouts mein nahi book se zarroor parh lena ye topic
(2) where TCP/IP Used?? difference bw IP n PC define PROM (3) STAGes in pipelined SRC diff bw serial and parallel transfer configuration of 1x8 memory Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines a) How many sets are there in the cache? b) How many bits of address are required to select a set in cache? 5) what is meant by abstraction from the user details by the operating system( YE KISI KO ATA HAI?) difference bw connection oriented and connection less compare 1D AND 2D write RTL for five instructions( TOTALLY DISAPPOINTED) movi R3,45 In R3,57 OUT R6 15 RET R3 ANDI R5 , R4. 5 Consider a 64KB direct-mapped cache with a line length of 32 bytes. (5 marks) a. Determine the number of bits in the address that refer to the byte within a cache line. b. Determine the number of bits in the address required to select the cache line Comparisons of FALCON-A and SRC (5 marks) How many platters are required for a 40GB disk if there are 1024 bytes/sector, 2048 sectors per track and 4096 tracks per platter (5) What is difference between hard disk, cylinder, sector (3 makrs) How to Virtual Memory work? Briefly define? (3 marks) Differences between RAID2 and RAID 3 (3 marks) What is Cache? How does it works? (3 marks) Cache Management (2 marks) What is EPROM (3 marks) What is difference between comma and semi-colon (2 marks) CS501 - Advance Computer Architecture(My paper on 19-02-11) Postby admin » Sat Feb 19, 2011 7:29 pm Format of the 1-Address instruction set-----2 Marks What attributes should have a device to qualify in order to be master device ---- 2 Marks What is mean when we use representation sing number in sing magnitude form? 2 Marks A network is suing the Bus topology if we replace the bus with switch what change will be take effects by this configuration…. 2 Marks What is ISA explain….. 2 marks Explain the relation ship between the Hard disk tracks, cylinders and sectors…3 marks Explain 1bit half adder function ……3 marks SRS assembly program for the following expiration..5 Marks Z = 13(A+B)-32(c-58) Latency of the ram is 30ns , if the time charge is 10ns and data pre change is 3 byte then find the band width…5 Mrks Compare the 1 x 8 bit Memory (1D) and 4 x 8 Memory (2D) 5 mark differentiate b/w RISC n CISC according to their instruction size and hardware, software? 5 marks. find total capacity of hard disk. (it was the same example that is on page no. 304 examle no 3 of our handouts.) 5 marks. what is the finction of Cntrol unit? 3 marks. what is the difference between control unit n data path? 2 marks what is the working of DMA controller? 5 marks define 64K x 1 static RAM chip? 5 marks. 5 marks question Define RAID 0 Calculate bandwidth Discuss problems of Pipelining 3 marks questions Differenciate Shared Medium and Switched Medium R[ra] = R[rb] - R[rc] Discuss its functionality Serial and Parallel data transfer Cache Direct Memory access approach 2 marks questions How you define microprogramming Interrupt driven I/O In Bus topology if we change bus to switch then what will happen MCQ RAID related 4-5 ISR related 4-5 Interrupt driven I/O 2-3 Cache 2-3 RISC and CISC 2 
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Linear Mode
